System 1

This is the first of many in a long line of 1802 based projects. This is basic design but it does the support an 1861 video chip, cassette I/O. The whole system is built with point to point wiring on Vero board. Unfortunately this system is no longer functional

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Every “real” computer needs a proper front panel

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Side and top view of system. The first card is the CPU card, the second is the interface to the front panel subsystem and the third is a 256 byte memory card. The motherboard also contains a few bits of the circuitry.

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4K byte memory card, the point to point wiring construction is much neater on this one.

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256 byte memory card with a switch to select bus or external power. Note power connector on right side of card. How many times can one person toggle in that monitor program!

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CPU Card: Revision B

Last Updated: October 31, 2005 11:13:27 AM

NO PCB YET

Revision B not produced yet. The bottom connector provides signals to the 1861/keyboard card that are not available on the standard system bus. The upper connector supports Front Panel functionality, again it provides signals not available on the bus. The complete system does not require a front panel to operate. This card replaces System-4 CPU card.

Description

The CPU card has several separate subsystems; clock generation, mode control, power on reset/run, address demultiplexing/decoding , 4K EPROM, and reset address remapping. The CPU card also has auxiliary connectors required for a full function front panel and an 1861 based video/keyboard system. Jumper blocks select -EF line mapping for the bus EF line, front panel EF line, 1861 Video EF and keyboard input EF line. Another set of jumpers selects the location of the EPROM within the address space. The last jumper block (VMA) determines if/how the address is remapped during reset from 0x0000 to the location occupied by the on board EPROM within the address space. See the operational description for details.

Issues/todo log

Date Description Status

Schematics, board layout, and operational description

Revision Production Date Schematic Layout Operational Description
A Jan. 11/05 cpu2-a.sch cpu2-a.brd Rev. A ops notes
B Current Development Board
*UNBUILT/UNTESTED*
cpu2-b.sch cpu2-b.brd Rev. B ops notes

CPU Card: Revision A

Last Updated: October 31, 2005 11:13:27 AM

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Revision A of the CPU card had a few mistakes and required some creative pin lifting, double socketing and rewiring to get it working. The bottom connector provides signals to the 1861/keyboard card that are not available on the standard system bus. The upper connector supports Front Panel functionality, again it provides signals not available on the bus. The complete system does not require a front panel to operate. This card replaces System-4 CPU card.

Description

The CPU card has several separate subsystems; clock generation, mode control, power on reset/run, address demultiplexing/decoding , 4K EPROM, and reset address remapping. The CPU card also has auxiliary connectors required for a full function front panel and an 1861 based video/keyboard system. Jumper blocks select -EF line mapping for the bus EF line, front panel EF line, 1861 Video EF and keyboard input EF line. Another set of jumpers selects the location of the EPROM within the address space. The last jumper block (VMA) determines if/how the address is remapped during reset from 0x0000 to the location occupied by the on board EPROM within the address space. See the operational description for details.

Issues/todo log

Date Description Status
Jan. 2005 SV6 pin 8 should be -reset not -run.

74LS123 should use Q (pin 13), not -Q (pin 4) to IC6
Gate A (PIn 1). 74LS123 CLR (Pin 3) should be tied
high, A (Pin 1) to 1232 RST (Pin 5)

1232 -ST (Pin 7) should be tied to 1802 Clock out (Pin
39) not to TPA.

74LS74 tie PRE (Pin 10) and D (Pin 12) high. CLK (pin
11) should be connected to A15 not GND.

Rewired

Schematic/Layout
Done

Rev. A

Rev. B

Jan. 2005 VMA, Boot/Remap silk screen entry touches pad Done Rev. B
Mar. 8/2005 Add jumper to disable automatic run after power on reset Done Rev. B

Schematics, board layout, and operational description

Revision Production Date Schematic Layout Operational Description
A Jan. 11/05 cpu2-a.sch cpu2-a.brd Rev. A ops notes
B Current Development Board
*UNBUILT/UNTESTED*
cpu2-b.sch cpu2-b.brd Rev. B ops notes

Breadboard Experiment

This is a recreation of the original test I ran sometime in 1977 with my brand new 1802. I wanted to try something that would require a minimum amount of work and see some sort of result.

1) Wire 0x7B by directly connecting D0 through D7 to the appropriate +5V and GND signals
2) Connect an LED and resistor to the Q signal
3) Connected up the power pins
4) using wires connected to the control lines reset the CPU and then set it to run
5) Apply pulse from signal generator (original test used a de-bounced switch) to CLOCK line
After 20 or so clock pulses the LED connected to the Q line lights up

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1802 with Led connected to Q signal and
LED connected to the CLOCK input signal.
Alligator clips are from pulse generator connected to CLOCK.
The Q LED is on the other LED is pulsing.