Board Construction Notes

Last Updated Mar. 08/2005

Board size 5.50 x 3.75

Bus Connector placement

Center location 0.2 x 1.875 (set Eagle grid to 0.025 to place connector and then restore to 0.05)

Restricted areas

Layer 41 and 42 place 3.00 x 0.15 polygons left and right bottom corners (next to bus connector) to prevent

traces from contacting card supports

LED Placement

Cathode (flat section) facing inward toward bus connector

5.2 (X axis) by

(y -axis)

0.3 Power – Label PWR 5.4 x .45

1.0 Aux 1 – Label xxx 5.4 x xxx

1.7 Aux 2

2.4 Aux 3

3.1 Aux 4

Eagle Library components

LED type 5MM

Resistors 207/7

Bypass capacitors C025-050×050

Tantalum capacitor placement .45 x 3.45 (+) closer to VCC

Board Labeling

NAME Label .05 x .05


XXX = Board name

# = board design (different types of similar function)

A = Revision level

All slik screen writing on layer 25

PC Board Silk Screen uses layers 20, 21, 25

Verify Process

Do ERC Check

Verify GND and VCC Connected at bus

Verify unconnected input pins on pin list

Build Process


Run Script


!!!Update file names and order number inside readme file before uploading zip file for production!!!